RESUME

Objective: Seeking a challenging career in R&D and innovation.

Education:

Research Papers (Published)

1. Jugal Kishore Sharma and G.V. Singh, "User Satisfaction based Measurement Model for Quality of Service and Fairness", National Conference on Mathematical Modeling and Optimization and Their Applications (OptiMA-2007), April 28-29, 2007.

2. Jugal Kishore Sharma and G.V. Singh, "Arrival Time and Queuing Delay Estimation", 3rd International Conference on Quality, Reliability and Infocom Technology (ICQRIT 2006), Dec 2-4, 2006.

3. Jugal Kishore Sharma and G.V. Singh, "Comprehensive Delay Tolerance based Fair Bandwidth Allocation", Proceedings of All India Seminar on Advances in Computer and Information Technology (ACIT-2006), March 11-12, 2006, pp12.

4. Jugal Kishore Sharma and G.V. Singh, "Delay Tolerance based Fair Bandwidth Allocation", Proceedings of 39th annual national convention of Computer Society of India, Dec 1-4, 2004, pp 35-45.

5. D K Lobiyal, Jugal Kishore Sharma and G.V. Singh, "IP address filtering to control congestion", 49th FID conference, New Delhi, 1998.

Research Papers (Submitted)

1. Jugal Kishore Sharma, "Viability of C-DOT Circuit Switches in IP Core" Submitted to C-DOT R&D Journal, 2007.

2. Kamal Kumar and Jugal Kishore Sharma, "Supporting Advanced Features on MAX Input Output Module", Submitted to C-DOT R&D Journal, 2007.

Reports Prepared:

1. Feasibility Report on designing the C-DOT DSS as packet switch, SGSN and GGSN to supplement GSM phase 2+ services.

2. Design document and message sequence charts to implement An Interface Initialization and An Interface Circuit Supervision features for GSM Phase 2+ services.

Overview

Experience: Over 10 years (Since May 1998 till date) in Premier Telecommunication R&D Institute, Centre for Development of Telematics (C-DOT), Govt. of India, New Delhi.

Responsibility:

Team Leader, Since May 2004

Senior Research Engineer, Oct 2002 to May 2004 and

Research Engineer, May 1998 to Oct 2002.

• Awarded PhD degree in March 2007, Jawaharlal Nehru University, New Delhi.

• Topic- “Adaptive Strategies for Improvement of Quality of Service in IP Telephony”.

• Five research papers published in International and National Conferences.

• Submitted two research papers.

• Research area - Quality of Service in IP Telephony.

• Worked in various projects in Telecommunication which include-

1. Element Management System

2. Next Generation Network (NGN).

3. Network/Element Management System.

4. Circuit Switching, Main Automatic Exchange (MAX),

High Erlang Capacity Switch (HECS).

Remote Switch Unit (RSU),

5. Global System for Mobile Communication (GSM).

Experience:

Organization: C-DOT, CENTRE FOR DEVELOPMENT OF TELEMATICS,

Telecom Technology Centre of Govt. of India, New Delhi.

Date of Joining: 27/5/1998 – Continuing.

Project: Network and Element Management System for Next Generation Networks
Role: Team Leader
Assignment: Specifications, Architecture and Development.

Project: IP based Converged Services Network
Role: Team Leader
Assignment: Specifications and Architecture.

Project: MAX Release Stabilization for X2_2_1_6
Role: Team Leader and Assistant Release Coordinator
Assignment: Co-ordination to stabilize the release X2_2_1_6 for C-DOT MAX

Project: MAX Release Stabilization for X2_2_1_8
Role: Team Leader and Assistant Release Coordinator
Assignment: Co-ordination to stabilize the release x2_2_1_8 for C-DOT MAX

Project: Enhanced Controller for Alarm Display panel (ECA)
Role: Team Leader

Description: Enhanced Controller for Alarm Display panel (ECA) is the Motorola 68302 processor based controller card for alarm display panel in C-DOT MAX circuit switch.
Assignment: To develop application software on ECA. The Application development had five features: 1) Processor Initialization 2) Operating System 3) Unit Initialization 4) Alarms raising, storing and clearing 5) Fault handling

Project: Remote Value Engineered Base Module (RVEBM) with E3 support
Role: Team Leader

Description: In High Erlang Capacity Switch (HECS) architecture, the link between Value Engineered Base Module (VEBM) and Value Engineered Central Module (VECM) is the E3 link, where as it is BUS in case of DSS-MAX architecture. The E3 support enables the same VEBM hardware to be equipped as Remote Switch Unit (RSU).
Assignment: To design the software so that the VEBM may work as RSU if equipped as RVEBM. It was designed with the following features: 1) Initialization 2) Transition from Normal to Stand Alone Mode 3) Transition from Stand Alone (SA) mode to Normal mode 4) Link status and alarm display

Project : High Erlang Capacity Switch (HECS)
Role: Team Leader

Description: HECS is based on Time-Time-Time switch (TTT) technology and its capacity is twice that of time-space-time (TST) switch technology based MAX.
Assignment: To design, test, debug and to solve the field problems of HECS in the following features: 1) Alarms, 2) Reports, 3) Call Killing, 4) Audits, and 5) Recovery

Project: Mobile Service Switching Centre based on DSS (DSS-MSC)
Role: Research Engineer, and after promotion as a Team Leader

Description: To develop MSC on DSS architecture with the motive “No change in hardware”.
Assignment: To design, develop, test, debug and solve the field problems in the following features. 1) Terminal fault tolerance, 2) Audits, 3) Dormant Subscriber buffer purge, 3) Call Killing, 4) A Interface Initialization, and 5) A Interface Circuit Supervision (blocking, unblocking, reset circuit, circuit group blocking, circuit group unblocking, unequip circuit procedures)

Ph.D. Research Work:

The vast convergence of all electronic communications over IP with diverse applications and services has great Quality of Service (QoS) requirements. The already laid infrastructure needs adaptive strategies, the complex and cost increasing strategies have lesser response and the Internet still supports a Best Effort service.

• A Realistic Measurement Model: We propose a realistic measurement model based on user satisfaction and user tolerance limit which is an acceptable yardstick to measure all varied services on a single platform. ITU-T Rec. G1010 (11/2001) acknowledges its importance. A coefficient of QoS and Fairness has been defined. A classification criteria for grouping the traffic with similar QoS requirements based on this measurement model has been proposed.

• QoS control architecture: A QoS control architecture based on Queuing delay and Queue size is defined. It maintains an equal ratio of delay to user tolerance limit as control action level one, it is a critical level after which a selective rerouting and selective dropping is done as control action level two and three.

• Queuing delay measurement: Queuing delay measurement is essential for delay based QoS control architecture. Noting the arrival time of individual items requires a vast memory space and computational power and on heavily loaded routers it is not feasible, we propose a delay estimation algorithm which estimates the queuing delay with an upper limit on the magnitude of absolute error. The algorithm is tunable; as higher the magnitude of absolute error lesser will be computational power and memory space, and is scalable because the computational time and memory space increase little with traffic growth. It adapts the available router capacities with the desired accuracy.

• Fairness: Fairness in QoS is very important and essential. Fairness means equal level of user satisfaction for all the application flows. We propose two QoS control strategies Delay Tolerance based Fair Bandwidth Allocation (DTFBA) and Comprehensive Delay Tolerance based Fair Bandwidth Allocation (CDTFBA) which fairly allocate bandwidth. This optimizes the output, maintains a uniform user satisfaction level, and makes the services predictable.

• Fairness in Delay and Delay Variation: It provides Fairness in Delay and Delay Variation. The equalized coefficient of QoS leaves a fair room to compensate Jitters, and provides a predictable QoS. The strategies reallocate and adjust Bandwidth periodically. The strategies are tunable and scalable to the time and space requirements. If the memory space and computational power is limited, CDTFBA is the choice, otherwise DTFBA is the choice.

• Simulator in C: We have designed our own simulator in ‘C’ language to analyze the performance of the strategies. The simulator creates a user defined network. The traffic flows of different rates are generated with Poisson arrival of packets and a normal distribution in packet size.

Result Analysis: We have analyzed the performance of DTFBA and CDTFBA under a projected set of operational conditions. The alternatives have been compared with the help of simulation to see which best meet a specified requirement. We have compared DTFBA, CDTFBA and Best Effort (BE) with their respective performances on the different values of tunable parameters under the same simulation environment and load. In addition to statistical analysis, to note how the system performances change dynamically over the time, and to read when the characteristics vary as a function of time, we have compared DTFBA, CDTFBA and BE with the help of a Graphical Analysis. The study reveals that the performance of DTFBA and CDTFBA is far better. Simulation results show that DTFBA and CDTFBA perform 126.41 times and 99.86 times better than BE respectively.